pin configuration output noninverting input output inverting input inverting input noninverting input ? 3 4 5 6 7 8 1 2 +v top view note: pin 4 connected to case amplifier no. 1 amplifier no. 2 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a dual high speed, implanted bifet op amp ad644 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features matched offset voltage matched offset voltage over temperature matched bias currents crosstalk C124 db at 1 khz low bias current: 35 pa max warmed up low offset voltage: 500 m v max low input voltage noise: 2 m v p-p high slew rate: 13 v/ m s low quiescent current: 4.5 ma max fast settling to 6 0.01%: 3 m s low total harmonic distortion: 0.0015% at 1 khz standard dual amplifier pinout available in hermetic metal can package and chip form mil-std-883b processing available single version available: ad544 product description the ad644 is a pair of matched high speed monolithic fet in- put operational amplifiers fabricated with the most advanced bi- polar, jfet and laser-trimming technologies. the ad644 offers matched bias currents that are significantly lower than currently available monolithic dual bifet operational amplifiers: 35 pa max, matched to 25 pa for the ad644k and l, 75 pa max matched to 35 pa for the AD644J and s. in addition, the offset voltage is laser trimmed to less than 0.5 mv, and matched to 0.25 mv for the ad644l, 1.0 mv and matched to 0.5 mv for the ad644k, utilizing analog devices laser-wafer trimming (lwt) process. the tight matching and temperature tracking between the op- erational amplifiers is achieved by ion-implanted jfets and laser-wafer trimming. ion-implantation permits the fabrication of precision, matched jfets on a monolithic bipolar chip. this process optimizes the ability to produce matched amplifiers which have lower initial bias currents than other popular bifet op amps. laser-wafer trimming each amplifiers input offset voltage assures tight initial match and superior ic processing guarantees offset voltage tracking over the temperature range. the ad644 is recommended for applications in which both excellent ac and dc performance is required. the matched am- plifiers provide a low cost solution to true wideband instrumen- tation amplifiers, low dc drift active filters and output amplifiers for four quadrant multiplying d/a converters such as the ad7541, 12-bit cmos dac. the ad644 is available in four versions: the j, k and l are specified over the 0 c to +70 c temperature range and the s over the C55 c to +125 c operating temperature range. all devices are packaged in the hermetically sealed, to-99 metal can or available in chip form. product highlights 1. the ad644 has tight side to side matching specifications to ensure high performance without matching individual devices. 2. analog devices, unlike some manufacturers, specifies each device for the maximum bias current at either input in the warmed-up condition, thus assuring the user that the ad644 will meet its published specifications in actual use. 3. laser-wafer-trimming reduces offset voltage to as low as 0.5 mv max matched side to side to 0.25 mv (ad644l), thus eliminating the need for external nulling. 4. improved bipolar and jfet processing on the ad644 result in the lowest matched bias current available in a high speed monolithic fet op amp. 5. low voltage noise (2 m v p-p) and high open loop gain enhance the ad644s performance as a precision op amp. 6. the high slew rate (13.0 v/ m s) and fast settling time to 0.01% (3.0 m s) make the ad644 ideal for d/a, a/d, sample- hold circuits and dual high speed integrators. 7. low harmonic distortion (0.0015%) and low crosstalk (C124 db) make the ad644 an ideal choice for stereo audio applications. 8. the standard dual amplifier pin out allows the ad644 to replace lower performance duals without redesign. 9. the ad644 is available in chip form.
ad644Cspecifications (@ +25 8 c and v s = 6 15 v dc) model AD644J ad644k ad644l ad644s min typ max min typ max min typ max min typ max units open loop gain v o = 10 v, r l 3 2 k w 30,000 50,000 50,000 50,000 v/v t min to t max , r l = 2 k w 20,000 40,000 40,000 20,000 v/v output characteristics voltage @ r l = 2 k w , t min to t max 6 10 12 6 10 12 6 10 12 6 10 12 v voltage @ r l = 10 k w , t min to t max 6 12 13 6 12 13 6 12 13 6 12 13 v short circuit current 25 25 25 25 ma frequency response unity gain small signal 2.0 2.0 2.0 2.0 mhz full power response 200 200 200 200 khz slew rate, unity gain 8.0 13.0 8.0 13.0 8.0 13.0 8.0 13.0 v/ m s total harmonic distortion 0.0015 0.0015 0.0015 0.0015 % input offset voltage 1 initial offset 2.0 1.0 0.5 1.0 mv input offset voltage t min to t max 3.5 2.0 1.0 3.5 mv input offset voltage vs. supply, t min to t max 200 100 100 100 m v/v input bias current 2 either input 10 75 10 35 10 35 10 35 pa offset current 10 5 5 5 pa matching characteristics 3 input offset voltage 1.0 0.5 0.25 0.5 mv input offset voltage t min to t max 3.5 2.0 1.0 3.5 mv input bias current 35 25 25 35 pa crosstalk C124 C124 C124 C124 db input impedance differential 10 12 i 610 12 i 610 12 i 610 12 i 6m w i pf common mode 10 12 i 310 12 i 310 12 i 310 12 i 3m w i pf input voltage range differential 4 20 20 20 20 v common mode 10 12 10 12 10 12 10 12 v common-mode rejection 76 80 80 80 db input noise voltage 0.1 hz to 10 hz 2222 m v p-p f = 10 hz 35 35 35 35 nv/ ? hz f = 100 hz 22 22 22 22 nv/ ? hz f = 1 khz 18 18 18 18 nv/ ? hz f = 10 khz 16 16 16 16 nv/ ? hz power supply rated performance 15 15 15 15 v operating 5 18 5 18 5 18 5 18 v quiescent current 3.5 4.5 3.5 4.5 3.5 4.5 3.5 4.5 ma temperature range operating, rated performance 0 +70 0 +70 0 +70 C55 +125 c storage C65 +150 C65 +150 C65 +150 C65 +150 c package option to-99 style (h-08b) AD644Jh ad644kh ad644lh ad644sh chips AD644Jchips ad644kchips ad644schips notes 1 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = +25 c. 2 bias current specifications are guaranteed at maximum at either input after 5 minutes of operation at t a = +25 c. for higher temperatures, the current doubles every 10 c. 3 matching is defined as the difference between parameters of the two amplifiers. 4 defined as voltage between inputs, such that neither exceeds 10 v from ground. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. specifications subject to change without notice. metalization photograph dimensions shown in inches and (mm). contact factory for latest dimensions. rev. a C2C
typical characteristicsCad644 C3C rev. a
ad644 rev. a C4C
ad644 rev. a C5C the fast settling time (3.0 m s to 0.01% for 20 v p-p step) and low offset voltage make the ad644 an excellent choice as an output amplifier for current output d/a converters such as the ad7541. the upper trace of the oscilloscope photograph of fig- ure 23b shows the settling characteristics of the ad644. the lower trace represents the input to figure 23a. the ad644 has been designed for fast settling to 0.01%, however, feedback components, circuit layout and circuit design must be carefully considered to obtain the optimum settling time. the circuit in figure 24 employs a 100 w isolation resistor which enables the amplifier to drive capacitive loads exceeding 500 pf; the resistor effectively isolates the high frequency feed- back from the load and stabilizes the circuit. low frequency feedback is returned to the amplifier summing junction via the low pass filter formed by the 100 w series resistor and the load capacitance, c l . the low input bias current (35 pa), low noise, high slew rate and high bandwidth characteristics of the ad644 make it suit- able for electrometer applications such as photodiode preampli- fiers and picoampere current-to-voltage converters. the use of guarding techniques in printed circuit board layout and con- struction is critical for achieving the ultimate in low leakage per- formance that the ad644 can deliver. the input guarding scheme shown in figure 25 will minimize leakage as much as possible. the same layout should be used on both sides of a double side board. the guard ring is connected to a low imped- ance potential at the same level as the inputs. high impedance signal lines should not be extended for any unnecessary length on a printed circuit; to minimize noise and leakage, such con- ductors should be replaced by rigid shielded cables. figure 25. board layout for guarding inputs input protection the ad644 is guaranteed for a maximum safe input potential equal to the power supply potential. the input stage design also allows differential input voltages of up to 1 volt while main- taining the full differential input resistance of 10 12 w . this makes the ad644 suitable for comparator situations employing a direct connection to high impedance source. many instrumentation situations, such as flame detectors in gas chromatographs, involve measurement of low level currents from high voltage sources. in such applications, a sensor fault condition may apply a very high potential to the input of the current-to-voltage converting amplifier. this possibility necessi- tates some form of input protection. many electrometer type devices, especially cmos designs, can require elaborate zener protection schemes which often compromise overall performance. the ad644 requires input protection only if the source is not current-limited, and as such is similar to many jfet-input designs. the failure mode would be overheating from excess current rather than voltage breakdown. if the source is not current-limited, all that is required is a resistor in series with the affected input terminal so that the maximum overload current is 1.0 ma (for example, 100 k w for a 100 volt overload). this simple scheme will cause no significant reduction in perfor- mance and give complete overload protection. figure 26 shows proper connections. figure 26. ad644 input protection
ad644 rev. a C6C c633bC5C1/85 printed in u.s.a. figure 27a illustrates the 10-bit digital-to-analog converter, ad7533, connected for bipolar operation. since the digital in- put can accept bipolar numbers and v ref can accept a bipolar analog input, the circuit can perform a 4-quadrant multiplying function. the photos exhibit the response to a step input at v ref . figure 27b is the large signal response and figure 27c is the small signal response. the output impedance of a cmos dac varies with the digital word thus changing the noise gain of the amplifier circuit. the effect will cause a nonlinearity the magnitude of which is depen- dent on the offset voltage of the amplifier. the ad644k with trimmed offset will minimize the effect. the schottky protection diodes recommended for use with many older cmos dacs are not required when using the ad644. active filters literature on active filter techniques and characteristics based on operational amplifiers is readily available. the successful ap- plication of an active filter however, depends on the component selection to achieve the desired performance. the ad644 is rec- ommended for filters in medical, instrumentation, data acquisi- tion and audio applications, because of its high gain bandwidth figure, symmetrical slewing, low noise, and low 1 offset voltage. the state variable filter (figure 28) is stable, easily tuned and is independent of circuit q and gain. the use of the ad644 with its low input bias current simplifies the resistor (r3, r4) selec- tion for the passband center frequency, circuit q and voltage gain. figure 28. band pass state variable filter the sample and hold circuit, shown in figure 29 is suitable for use with 8-bit a/d converters. the acquisition time using a 3900 pf capacitor and fast cmos spst (adg200) switch is 15 m s. the droop rate is very low 25 10 C9 v/ m s due to the low input bias currents of the ad644. care should be taken to minimize leakage paths. leakages around the hold capacitor will increase the droop rate and degrade performance. figure 29. sample and hold circuit the ad644 in the circuit of figure 30 provides highly accurate signal conditioning with high frequency input signals. it pro- vides an offset voltage drift of 10 m v/ c, cmrr of 80 db over the range of dc to 10 khz and a bandwidth of 200 khz (C3 db) at 1 v p-p output. the circuit of figure 30 can be configured for a gain range of 2 to 1000 with a typical nonlinearity of 0.01% at a gain of 10. figure 30. wide bandwidth instrumentation amplifier outline dimensions dimensions shown in inches and (mm).
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